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NCP1631
Given the regulation low bandwidth of the PFC systems,
(V CONTROL ) and then (V REGUL ) are slow varying signals.
Hence, the line current absorbed by each phase is:
From this equation, we can check that if V pin7 (BO
voltage) is 1 V and R t is 20 k W (I pin3 = 50 m A) that the
on ? time is 20 m s as given by parameter T on1 .
I in(phase1) + I in(phase2) + k V in
(eq. 6)
Since:
C t V REGUL
2 L I t
C t V REGUL
I t
k BO +
t 1 + T on ( m s) + 50 n
R t 2
V pin7 2
(R t ) 2 V REGUL
I in(rms) ^
26.9 @ 10 12 L k BO 2 V in,rms
(R t ) 2 V REGUL
P in,avg ^
26.9 @ 10 12 L k BO 2
where: k + constant +
Hence, the input current is then proportional to the input
voltage and the ac line current is properly shaped.
One can note that this analysis is also valid for CrM
operation that is just a particular case of this functioning
where (t 3 =0), which leads to (t 1 +t 2 =T sw ) and
(V TON =V REGUL ). That is why the NCP1631 automatically
adapts to the conditions and jumps from DCM and CrM
(and vice versa) without power factor degradation and
without discontinuity in the power delivery.
The charging current I t is internally processed to be
proportional to the square of the line magnitude. Its value
is however programmed by the pin 3 resistor to adjust the
available on ? time as defined by the T on1 to T on4 parameters
of the data sheet.
From these data, we can deduce:
(eq. 7)
V REGUL(max) + 1.66 V
T on +
2 2 V in(rms)
V pin7 + p k BO
where k BO is the scale down factor of the BO sensing
network
R bo2
R bo1 ) R bo2
(see Brown ? out section)
We can deduce the total input current value and the
average input power:
(eq. 8)
(eq. 9)
timing capacitor
s aw ? too th
PWM
comparator
+
?
to PWM latch
V REGUL
R1
+
?
OA1
C1
Vton
S3
SKIP
OV P
OF F
IN 1
OC P
0.5*
(I se nse
? 210 m )
S1
V BOcomp
(from BO block)
pfcOK
? > V ton d u ring (t1+t2) S2
? > 0 V d u ring t3 (d e a d ? time)
? > V ton *(t1+t2)/T in average
DT
(high during dead ? time)
In ? rus h
The integrator OA1 amplifies the error between V REGUL and
IN1 so that in average, (V TON *(t 1 +t 2 )/T sw ) equates V REGUL .
Figure 6. PWM Circuit and Timing Diagram
The “V TON processing circuit” is “informed” when there
is an OVP condition or a skip sequence, not to
over ? dimension V TON in that conditions. Otherwise, an
OVP sequence or a skipped cycle would be viewed as a
“normal” dead ? time phase by the circuit and V TON would
inappropriately increase to compensate it. (Refer to
Figure 7).
Figure 7. V TON Processing Circuit
The output of the “V TON processing circuit” is also
grounded when the circuit is in OFF state to discharge the
capacitor C1 and initialize it for the next active phase.
Finally, the “V TON ” is not allowed to be further increased
compared to V REGUL when the circuit has not completed
the start ? up phase (pfcOK low) and if V BOcomp from the
brown ? out block is high (refer to brown ? out section for
more information).
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